Prescott : "LA FIERA DEL BUG"
le nuove cpu , intel amd via ibm che siano hanno sempre dei bug , ma questo ne ha veramente tanti , eccovi un estratto :
R1 X X No Fix Transaction Is Not Retried after BINIT#
R2 X X No Fix Invalid Opcode 0FFFh Requires a ModRM Byte
R3 X X No Fix Processor May Hang Due to Speculative Page Walks to Non-Existent System Memory
R4 X X No Fix Memory Type of the Load Lock Different from Its Corresponding Store Unlock
R5 X X No Fix Machine Check Architecture Error Reporting and Recovery May Not Work As Expected
R6 X X No Fix Debug Mechanisms May Not Function as Expected
R7 X X No Fix Cascading of Performance Counters Does Not Work Correctly When Forced Overflow Is
Enabled
R8 X X No Fix EMON Event Counting of x87 Loads May Not Work As Expected
R9 X X No Fix System Bus Interrupt Messages without Data Which Receive a HardFailure Response May
Hang the Processor
R10 X X No Fix The Processor Signals Page-Fault Exception (#PF) Instead of Alignment Check Exception
(#AC) on an Unlocked CMPXCHG8B Instruction
R11 X X No Fix FSW May Not Be Completely Restored after Page Fault on FRSTOR or FLDENV Instructions
R12 X X No Fix Processor Issues Inconsistent Transaction Size Attributes for Locked Operation
R13 X X No Fix When the Processor Is in the System Management Mode (SMM), Debug Registers May Be
Fully Writeable
R14 X X No Fix Shutdown and IERR# May Result Due to a Machine Check Exception on a Hyper-Threading
Technology Enabled Processor
R15 X X No Fix Processor May Hang under Certain Frequencies and 12.5% STPCLK# Duty Cycle
R16 X X No Fix
System May Hang if a Fatal Cache Error Causes Bus Write Line (BWL) Transaction to Occur
to the Same Cache Line Address as an Outstanding Bus Read Line (BRL) or Bus Read-
Invalidate Line (BRIL}
R17 X X No Fix A Write to APIC Registers Sometimes May Appear to Have Not Occurred
R18 X Fixed Some Front Side Bus I/O Specifications are not Met
R19 X X No Fix Parity Error in the L1 Cache May Cause the Processor to Hang
R20 X Fixed BPM4# Signal Not Being Asserted According to Specification
R21 X X No Fix Sequence of Locked Operations Can Cause Two Threads to Receive Stale Data and Cause
Application Hang
R22 X X Plan Fix A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause an Incorrect
Address to be Reported to the #GP Exception Handler
R23 X X No Fix Bus Locks and SMC Detection May Cause the Processor to Temporarily Hang
R24 X Fixed PWRGOOD and TAP Signals Maximum Input Hysteresis Higher Than Specified
R25 X X Plan Fix Incorrect Physical Address Size Returned by CPUID Instruction
R26 X X No Fix Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint is set on an FP
Instruction
R27 X X No Fix xAPIC May Not Report Some Illegal Vector Errors
R28 X X Plan Fix Enabling No-Eviction Mode (NEM) May Prevent the Operation of the Second Logical
Processor in a Hyper-Threading Technology Enabled Processor
R29 X X Plan Fix Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation is Enabled in a Processor
Supporting Hyper-Threading Technology
R30 X X No Fix Memory Aliasing of Pages as Uncacheable Memory Type and Write Back (WB) May Hang the
System
R31 X X Plan Fix Interactions Between the Instruction Translation Lookaside Buffer (ITLB) and the Instruction
Streaming Buffer May Cause Unpredictable Software Behavior
per saperne di piu' :
http://www.intel.com/design/pentium4...t/30235203.pdf
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