Toshiba lancia gli SSD NVMe XG5-P - [NEWS]

[pippo369]

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[frakka]

Direi molto promettente... 1Tb di ssd "Single chip" lascia prevedere scenari interessanti e un aumento rapido delle capacità complessive, magari nelle versioni PCI-Ex.

[virgolanera]

Personalmente queste BiCS non mi convincono affatto sotto l'aspetto della durata.

[frakka]

Ah... Male, malissimo.

[giostark]

Personalmente queste BiCS non mi convincono affatto sotto l'aspetto della durata.

...ho letto questo estratto di un libro sulle NAND 3D e mi son fatto l'idea che le 3D FG (floating gate) opportunamente rivisitate offrano vantaggi maggiori in termini di durata , affidabilita' e performance (programmano molto piu' rapidamente la cella e sono meno stressate). Ma Toshiba probabilmente per questione di costi , visto che le FG occupano il 60% in piu' dello spazio ( e chissà quali tecnologie dovrebbero sviluppare per poterla sfruttare a pieno) , stanno tentando di ottimizzare le celle TC (charge trap).
3D Flash Memories : The first book to focus on 3D flash memories
http://www.springer.com/cda/content/...089-p177817210

Tra i tanti problemi , sostanzialmente quelli principali sembrano essere questi. In ultrasunto.

2.7.1
Vertical Charge Loss Through Top and Bottom Oxides
A constraint for the 3D vertical arrays, not present in planar devices, is that the
charge-trap layer cannot be easily interrupted between layers. This fact creates
additional leakage paths for the charge, from each cell’s active area towards other
cells on the same string, as schematically illustrated in Fig. 2.18. In addition to
vertical charge loss through Top and Bottom oxides (along Y axis), lateral charge
leakage (along X axis) represents an extra source of retention loss for cells in 3D
vertical arrays, which should be carefully considered for the reliability assessment
of the technology

2.10
3D-CT Versus 3D-FG
In this section a final comparison between 3D CT and 3D FG in terms of perfor-
mance and reliability is reported. For the comparison of the structures, vertical
schematic of the conventional 3D CT structure and 3D FG cell are shown in
Fig. 2.39 [34]. Unlike planar CT device, the CT nitride layer in a string of the
conventional 3D CT is continuously connected from top to bottom CGs along the
channel side, and it acts as a charge spreading path, which is an unavoidable
problem of 3D CT cell. As a result, this causes degradation of data retention
characteristics and poor distribution of cell state. In 3D FG cells, on the contrary,
the FG is completely isolated by the tunnel oxide and the Inter Poly Dielectric
(IPD). This approach allows obtaining a significantly reliable structure, able to
contain charges without any problem related to leakage paths [34].
In order to compare the cell size, DC-SF as 3D FG and BiCS/TCAT as 3D CT
are considered. The effective cell size is estimated and plotted in Fig. 2.40 as a
function of the number of stacked cells. Even if the physical size of DC-SF cell is
assumed to be 54 % larger than that of conventional BiCS/TCAT, DC-SF allows
fabricating 1 Tb arrays with 3 bit/cell and 64 stacked cells or 2 Tb arrays with 3
bit/cell and 128 stacked cells, thanks to the small FG-FG interference.
Moreover, 3D FG ensure reliable retention characteristics and lower operation
voltage than that of conventional 3D CT [34]. As a result, the 3D FG structure
allows highly enhanced device performance for 3D NAND flash memory compared
to 3D CT. In the following, a summary of 3D FG advantages and disadvantages
compared to 3D CT is reported ...

Advantages of 3D FG:
• Lower charge spreading resulting in less read errors, and consequently less ECC
intervention, in particular in multilevel architectures;
• better data retention because of a more stable charge into the storage layer;
• direct connection between channel poly and p-well, allowing bulk erase (no
GIDL).
Disadvantages of 3D FG:
• Larger cell size;
• larger 3D pillar due to the presence of the floating gate, and hence lower
scalability;
• floating gate coupling effect: even if the S-SCG structure can sufficiently sup-
press the indirect interference effect, direct coupling remains a very serious
problem that strongly reduces the programming speed.
Even if 3D FG shows a relevant number of reliability advantages compared to
3D CT, the higher scalability still makes 3D CT the most attractive solution for the
integration in hyper-scaled arrays. Moreover, it must be pointed out that enhanced
programming algorithms and error correction techniques allows mitigating the
previously described reliability issues.

Pare che Toshiba incrementando gli spazi tra le celle cilindriche abbia migliorato la gestione elettrica dichiarando una migliore performance di durata (affidabilita' - realiability) rispetto alle prime versioni dei loro chip verticali.

Questa info pare coerente con l'articolo:


Riguardo la durata pare comunque che sia attestata a diversi anni a patto che le temperature di funzionamento siano decenti:


Il problema dei cicli di scrittura rimane legato agli stessi canali di ossidazione delle celle e a come sono realizzati. Insomma pare che ogni tecnologia si porti dietro la solita sterminata serie di problemi.

[virgolanera]

In linea di massima, per SSD PCIe NVMe di fascia alta con capacità fino ad 1TB, ritengo sia sicuramente da preferire la soluzione Floating Gate.
Per le capacità maggiori, attualmente, mi affiderei ancora a soluzioni meno veloci (SATA) ma più durature come le NAND Flash di tipo planare MLC.